Semiconductor integrated circuit technology has rapidly progressed. For example, in the case of dynamic memory, memory chips with a capacity of 1 though 4 Mbit have been already put into mass production and ultra large integration memory chips such as 16 Mb or 64 Mb memory are now being developed. Such ultra large integration technology is applied to a logic circuit as well as a memory circuit, and a variety of functional logic integrated circuits represented by 32 bit CPU or 64 bit CPU are also under development.
In these logic circuits, an arithmetic operation is carried out by using digital signals, i.e., binary signals composed of 1 and 0. For example, a Neumann method is adopted for a computer, where commands are executed one by one according to a predetermined program. Although simple numerical calculations can be carried out at very high speed by this method, it takes a lot of time to perform the pattern recognition or image processing. Furthermore, this method is not suitable for information processing such as association of ideas, memorizing and learning, which is mankind's strongest point. In spite of a lot of research and development activities for software technology, notable results have not been produced yet.
There has been another stream of research to get rid of these difficulties at once and then to construct a computer which imitates arithmetic operations of the brain, i.e. neuron circuit computer (neural computer) by studying brain functions of living things. This kind of research began in the 1940s and has become very active in last several years based on the fact that the progress in LSI technology may make it possible to realize the hardware of a neuron computer.
However, the present semiconductor LSI technology still has too many problems to put it into practice. This is described more concretely. For example, in order to make the hardware with the function of one human neuron cell (neuron), a circuit must be constructed by combining a lot of semiconductor elements. In other words, it is very difficult to construct the practical number of neurons on a semiconductor chip.
The main purpose of this invention is to provide a semiconductor device which realizes the function of a neuron using a single MOS type semiconductor element. Before a detailed explanation of the invention is given, the function which is required for one neuron and the difficulties associated with the construction of a neuron using current technologies are described.
FIG. 19 is a schematic representation illustrating the function of a neuron cell, i.e., neuron, which was proposed by McCumllock and Pitts as a mathematical model of neuron (Bull. Math. Biophys., Vol. 5, p. 115 (1943)). At present, the studies are being carried out actively to construct a neuron computer by realizing this model with semiconductor circuits. V.sub.1, V.sub.2, V.sub.3, . . . , V.sub.n are n input signals defined as, for example, magnitudes of voltages, and correspond to signals transferred from other neurons. W.sub.1, W.sub.2, W.sub.3, . . . , W.sub.n are coefficients representing the coupling strengths between neurons, and are biologically called synapse couplings. The function of this neuron is simple. When the value Z, linear sum of the product of each input V.sub.i and weight W.sub.i (i=1-n), becomes larger than a predetermined threshold value V.sub.TH.sup.., the neuron outputs 1; on the other hand, 0 when Z is less than V.sub.TH.sup... The numerical expression is as follows: ##EQU1##
FIG. 19(b) shows the relationship between Z and V.sub.out. The output is 1 when Z is large enough as compared with V.sub.TH.sup.. and 0 when Z is small enough.
Next, an example of the circuits to realize the above-mentioned function using conventional semiconductor technology is shown in FIG. 20. In the figure, 102-1, 102-2 and 102-3 denote operational amplifiers. FIG. 20(a) shows a circuit to obtain Z by adding the product of input signal V.sub.i (i=1-n) and weight W.sub.i. I.sub.i denotes electric current flowing through R.sub.i. From I.sub.i =V.sub.i /R.sub.i, ##EQU2## the output voltage V.sub.a of the operational amplifier 102-1 is given by ##EQU3## Since I.sub.b is given by -V.sub.a /R, I.sub.a and I.sub.b have the same magnitude (I.sub.a =I.sub.b) and the opposite direction of flow, leading to the expression: ##EQU4## By the comparison between Eqs. (1') and (4'), the weight coefficient W.sub.i is found to be R/R.sub.i and therefore determined by the resistance. The circuit shown in FIG. 20(a) is a circuit to generate the voltage representing the linear sum of input signals obtained by summing up electric currents. FIG. 20(b) is an example of circuit to convert the value of Z into V.sub.out, where Z is connected to a non-inversion input terminal of operational amplifier 102-3. Since an operational amplifier is an amplifier having a large voltage amplification (gain), V.sub.out =V.sup.+ when Z&gt;E.sub..theta. and V.sub.out =V.sup.- when Z&lt;E.sub..theta., as shown in FIG. 20(c). Here, V.sup.+ and V.sup.= are the maximum and the minimum values of outputs which are determined by power supply voltage supplied to the operational amplifier. The value of V.sub.TH.sup.. can be changed by varying the voltage E.sub..theta. applied to non-inversion terminal. One of the problems of the circuit shown in FIGS. 20(a) and (b) is such that a lot of semiconductor elements are required to construct a neuron. Three operational amplifiers are used in the circuit of the figure and therefore 30 transistors are necessary since at least 10 transistors are usually required to construct one operational amplifier. And since the sum operation is made on the basis of electric current mode, a large amount of current always flows, resulting in large power dissipation. Namely, one neuron not only occupies a large area on a chip but also dissipates much power. Therefore, it is difficult to attain large scale integration. Even if large scale integration can be attained by shrinking the dimensions of transistor, it is almost impossible to construct a practical integrated circuit because of high density of the power dissipation.
Conventionally, source-follower circuits were widely used as circuits for the efficient driving of low impedance loads. Such a conventional circuit is depicted in FIG. 21. This diagram indicates a source-follower circuit comprising 1 NMOS transistor 2121 and a load resistance (R.sub.L) 2122; the drive load 2123 is assumed to be C.sub.out. If the resistance during the ON state of the NMOS transistor is assumed to be R.sub.ON, then V.sub.out is calculated according to the following formula: ##EQU5## Herein, R.sub.ON is a resistance determined by the gate source differential voltage V.sub.GS (=V.sub.in -V.sub.out). R.sub.L is set to a sufficiently high value, and when R.sub.L &gt;&gt;R.sub.ON, formula (1) is simplified to V.sub.out =V.sub.DD ; however, in actuality, when V.sub.out approaches V.sub.in, and the state shown in the formula: EQU V.sub.GS =V.sub.in -V.sub.out .apprxeq.V.sub.T
(V.sub.T indicates the threshold value of the NMOS transistor) is reached, the NMOS transistor changes to the OFF state, so that R.sub.ON rapidly reaches a high value. That is to say, the situation is as shown in the following formula: EQU V.sub.in -V.sub.out .apprxeq.V.sub.T
that is to say EQU V.sub.out =V.sub.in -V.sub.T ( 1)
is reached, and the output settles at a certain value. Even if V.sub.T is set equal to 0, V.sub.out will be equal to V.sub.in, and the transistor acts as a linear amplifier of voltage gain 1. In order to rapidly charge a large load capacitance C.sub.out, it is preferable to obtain a sufficiently large W/L of the transistor. (W indicates channel width, while L indicates channel length).
At this time, the gate capacitance of the MOS transistor is Cox.multidot.L.multidot.W, and increases in proportion to the product of L and W. (Cox indicates the capacitance with respect to a surface area unit of the gate). However, the voltage placed on both ends of the gate oxide film is essentially 0, so that the charge stored in this gate capacitance is, in actuality, 0, and accordingly, the effective input capacitance of the circuit of FIG. 21 seen from V.sub.in is essentially 0. That is to say, even if a large load capacitance (low impedance load) is carried on the output side of the circuit of FIG. 21, only a very small capacitance is apparent from the input side (the V.sub.in side) (high input impedance), so that such a circuit type has been widely known as an impedance conversion circuit. Such a circuit is extremely convenient for driving a large capacitance.
The threshold value of the NMOS transistor is set to V.sub.T =0, and when a fixed positive voltage V.sub.in is inputted into the circuit of FIG. 21, a fixed potential output V.sub.out =V.sub.in is maintained.
When this is done, a current EQU I.sub.n =V.sub.out /R.sub.L ( 2)
is caused to flow in this circuit, and power equalling V.sub.out2 /R.sub.L is consumed. In order to reduce this consumption current, R.sub.L must be increased. Here, if the input voltage changes from the positive fixed value V.sub.in to 0, then the change in V.sub.out at this time is approximately as shown in FIG. 22; it decreases at time constant R.sub.L .multidot.C.sub.out, and approaches 0. That is to say, the time period in which the output level conforms to the input and changes to the low potential side shortens in proportion to R.sub.L. That is to say, in order to increase the speed of the circuit, it is preferable that the R.sub.L be as small as possible.
However, when R.sub.L is reduced, as is clear from formula (2), the current value at the time at which the fixed voltage is maintained is increased, and the consumption current increases. Moreover, as can be understood from formula (1), the level of V.sub.out is lowered, and at R.sub.ON &gt;&gt;R.sub.L, V.sub.out is approximately equal to 0. That is to say, the effect of this is to reduce the voltage gain of the amplifier of FIG. 21 in a striking manner.
The present invention was created in order to solve the problems stated above; it has as an object thereof to provide a semiconductor device which makes possible almost zero steady state consumption power of the source-follower circuit, is moreover capable of being operated at high speed, and is further accompanied by no reduction at all in voltage gain.